Three-dimensional semiconductor integrated circuit devices have been known, in which two or more layers of wafers, each having a semi-conductor device or semiconductor integrated circuit device previously formed therein, are stacked vertically and the vertically-arranged semiconductor devices or semiconductor integrated circuit devices are electrically connected with each other via vertical wiring. For example, Japanese Patent Laid-Open Publication No. HEI-11-261001 discloses a method for manufacturing a three-dimensional semiconductor integrated circuit device, in accordance with which trenches (i.e., deep grooves) are formed in an upper-layer wafer having a semiconductor device or semiconductor integrated circuit device formed therein, wiring is embedded in each of the trenches of the upper-layer wafer, then a bump is formed on an end surface of each of the embedded wiring so that a lower-layer wafer, opposed to the upper-layer wafer and also having a semiconductor device or semiconductor integrated circuit device previously formed therein, is fixed to the upper-layer wafer at the bumps, and then an insulating adhesive is injected between the two stacked wafers, fixed together only at the bumps, to thereby manufacture a three-dimensional semiconductor integrated circuit device.
Prior to injecting the insulating adhesive between the two vertically-stacked wafers (collectively called “wafer stack”) in accordance with the disclosed manufacturing method, all outer surface regions of each of the stacked wafer are sealed with a sealing section (sealing frame or sealing wall) except for an outer surface region corresponding to an adhesive injection port formed in the sealing section, and then the fixed-together stacked wafers are placed and held in a receptacle. After that, the interior of the receptacle is evacuated to be turned into a vacuum state. Subsequently, the stacked wafers are lowered so as to immerse the adhesive injection port in the adhesive. Then, the interior of the receptacle is brought back to the atmospheric pressure level with the adhesive injection port still kept immersed in the adhesive, and thus, a pressure difference is produced between the gaps between the stacked wafers and the interior of the receptacle so that the adhesive is injected from the adhesive injection port into the gaps. Consequently, the three-dimensional semiconductor integrated circuit device is strengthened by hardening of the adhesive injected into the gaps, but also the electric wiring is reliably sealed up.
In the case where the technique of the HEI-11-261001 publication is employed, all the outer surface regions of the stacked wafers, other than the surface region corresponding to the adhesive injection port, have to be sealed with the sealing section as noted above, which unavoidably increases the number of necessary processing steps. Further, portions of the stacked wafers located above and below the sealing section and peripheral edge portions of the wafers would be wasted, and the adhesive may not be injected up to portions of the wafers opposite and remote from the adhesive injection port.
Further, with the disclosed technique where the adhesive injection port is provided at a single location near one end of the wafer stack, the adhesive has to travel a very long distance from the injection port (the longest necessary traveling distance is almost equal to the diameter of the wafer stack), requiring a long adhesive injection time. If the necessary traveling distance of the injected adhesive is very long, a great difference in the traveling time of the adhesive, and hence non-uniformity in the injected amount of the adhesive, would result between portions of the wafer stack near the adhesive injection port and portions of the wafer stack remote from the adhesive injection port; in addition, it would become difficult to adjust the viscosity of the adhesive. Because the wafer diameter is getting bigger and bigger nowadays in the field of the semiconductor technology, it is apparent that the above-identified problems with the disclosed technique, such as the increased adhesive injection time, will become more and more prominent.
Furthermore, in the technique of the HEI-11-261001 publication, a particular mechanism has been necessary for vertically moving the wafer stack in the receptacle. There has also been a demand that the wafer stack prior to the adhesive injection be avoided from movement and mechanical contact with the outside as much as possible in order to protect microprocessed portions of the wafers.